Low voltage class ab transconductor circuits

ABSTRACT

A class AB transconductor circuit comprises complementary PMOS and NMOS transistors ( 10, 12 ) having their source-drain paths connected in series between first and second voltage supply rails ( 14, 16 ). An output terminal ( 20 ) is coupled to a junction of said series connected source-drain paths. Gate electrodes of the PMOS and NMOS transistors are coupled to an input terminal ( 18 ) by way of respective first and second paths each of which includes first and second bias voltage supply sources ( 32, 34 ). The quiescent gate voltages of the PMOS and NMOS are offset from the quiescent input voltage by the equal and opposite voltages (V b ) of the first and second bias voltage supply sources thereby reducing the apparent threshold voltage (V t ′) of the PMOS and NMOS transistors by the value of the bias voltage supply sources. Balanced class AB transconductor circuits are also disclosed.

The present invention relates to low voltage class AB transconductorcircuits having application in gyrator channel filters for low powerwireless transceivers/receivers which may be fabricated as integratedcircuits.

Class AB transconductors fabricated using integrated CMOS transistorshave been successfully used in gyrator channel filters for modern lowpower wireless transceivers/receivers having application in Bluetoothand Zigbee. In order to operate optimally, the CMOS transistors requirea supply voltage of about four times the CMOS gate threshold voltage.This criterion is becoming difficult to achieve in newer sub-micronintegrating processes because leakage in the logic gates isnecessitating higher gate threshold voltages which at least in theoryrequire higher supply voltages if the criterion is to be followed.

U.S. Pat. No. 6,031,423 discloses a rail-to-rail op amp (operationalamplifier) which includes a N-channel input stage and a P-channel inputstage for receiving respectively an inverting input and a non-invertinginput. The N-channel input stage comprises a set of N-channel MOStransistors and the P-channel input stage comprises a set of P-channelMOS transistors. When operating in a differential mode as one inputvoltage increases the other input voltage decreases so that there is nodamaging substrate current. However when operating in a common mode inwhich both signal voltages are increasing and the transistors of theP-channel input stage are turning-off, damaging substrate currentoccurs. In order to protect the transistors of the P-channel input stagethe threshold voltage is reduced by creating a negative bulk-sourcevoltage, for example by subtracting the source voltage from the bulkvoltage, causing a reduction in the damaging current flowing through thesubstrate when the current through the P-channel input stage decreases.By protecting the transistors of the P-channel input stage it ispossible to achieve rail-to-rail operation at a reduced supply currentwhile minimizing damaging current through the substrate. This method ofprotecting a P-channel transistor is known in the art as changing theback gate voltage on the N-well of the transistor. U.S. Pat. No.6,031,423 does not disclose or suggest how the threshold voltages ofNMOS and PMOS transistors can be reduced in a class AB transconductorcircuit.

U.S. Pat. No. 6,456,157 B1 discloses a compensation circuit forregulating transistor threshold voltages in integrated circuits. Thecompensation circuit includes a transistor, a current source and a gatereference voltage supply. The transistor is biased to provide a wellbias voltage, or back gate voltage, which is coupled to transistors on acommon integrated circuit. More particularly the current source forcescurrent into the drain of the transistor causing its back gate to beforward biased and adjusting the back gate bias voltage. Thisspecification states that the compensation technique disclosed can beused to control the back gate voltage for NMOS target transistors (usinga NMOS compensation circuit) and for PMOS target transistors (using aPMOS compensation circuit). However there is no provision forcompensating NMOS and PMOS transistors simultaneously where one or othertype of transistor has no well.

It is an object of the present invention to be able to compensatesimultaneously NMOS and PMOS transistors used in a class ABtransconductor circuit, where one or other type of transistor has nowell.

According to one aspect of the present invention there is provided aclass AB transconductor circuit comprising complementary PMOS and NMOStransistors having their source-drain paths connected in series betweenfirst and second voltage supply rails, an output terminal coupled to ajunction of said series connected source-drain paths, and their gateelectrodes coupled to an input terminal by way of respective first andsecond paths, wherein first and second bias voltage supply means arerespectively provided in the first and second paths.

According to a second aspect of the present invention there is provideda balanced class AB transconductor circuit comprising first and secondtransconductor circuits made in accordance with the first aspect of thepresent invention, balanced inputs being applied to the respective inputterminals and balanced outputs being derived from the respective outputterminals.

According to a third aspect of the present invention there is providedan integrated circuit comprising a class AB transconductor circuit orbalanced class AB transconductor circuit made in accordance with thefirst or second aspect of the present invention.

According to a fourth aspect of the present invention there is provideda transceiver comprising a class AB transconductor circuit made inaccordance with the first or second aspect of the present invention.

The present invention will now be described, by way of example, withreference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of a class AB transconductor suitable foruse in current CMOS technology,

FIGS. 2 and 3 are circuit diagrams explaining the extreme conditions ofthe useful linear range of the transconductor shown in FIG. 1,

FIG. 4 is a conceptual circuit diagram of a class AB transconductor madein accordance with the present invention,

FIGS. 5 and 6 are conceptual circuit diagrams illustrating saturatedoperation of the class AB transconductor shown in FIG. 4 over the wholeoutput current range of ±4J,

FIG. 7 is a circuit diagram of an embodiment of a single ended class ABtransconductor made in accordance with the present invention,

FIG. 8 is a circuit diagram of an embodiment of a balanced class ABtransconductor made in accordance with the present invention,

FIG. 9 is a circuit diagram of another embodiment of a balanced class ABtransconductor made in accordance with the present invention, and

FIG. 10 is a block schematic diagram of a transceiver having a polyphasefilter comprising balanced gyrators which include balanced class ABtransconductors made in accordance with the present invention.

In the drawings the same reference numerals have been used to indicatecorresponding features.

In order to illustrate the supply voltage versus threshold voltageproblem in CMOS processes as they enter what is termed the deepsub-micron era a comparison is made between the supply and thresholdvoltages of typical currently available CMOS transistors and of CMOStransistors produced by an anticipated future process. Process supplyThreshold voltage Process Technology (μm) voltage V_(dd) (V) V_(t) (V)identification 0.18 1.8 0.35 Current 0.05 0.6 0.20 Future

From the comparison it can be seen that the ratio V_(dd)/V_(t) for thecurrent technology is of the order of 5, which is not unlike olderprocesses having supply voltages of 5V and a V_(dd)/V_(t) ratio of morethan 6, whereas for the anticipated future technology the ratio is 3.Since the threshold voltage is falling more slowly than the supplyvoltage it has been suggested that leakage problems in logic gates infuture processes may force the use of even higher threshold voltageswhich will have an unfavourable effect on the V_(dd)/V_(t) ratio.

Referring to FIG. 1 the illustrated class AB transconductor suitable foruse with current CMOS processing comprises a PMOS transistor 10 and aNMOS transistor 12 whose source-drain paths are connected in seriesbetween power supply rails 14, 16. The supply rail 14 is at a voltageV_(dda). The gate electrodes of the transistors 10, 12 are connected toa junction 18 to which an input signal v_(in) is applied. An outputsignal I_(out) is derived from a junction 20 of the drain electrodes ofthe transistors 10, 12.

For ease of the following explanation it will be assumed that thetransistors 10, 12 have an ideal square-law saturated behaviour andidentical parameters. Thus for a quiescent input voltage V_(dda)/2producing equal currents J in the transistors 10, 12, a zero outputcurrent is obtained.

Referring to FIGS. 2 and 3, the class AB transconductor shown in FIG. 1is terminated by another identical transconductor comprising a PMOStransistor 22 and a NMOS transistor 24 whose source-drain paths areconnected in series. The gate electrodes of the transistors 22, 24 areconnected to a junction 26 which is connected to the output junction 20of the class AB transconductor, that is CMOS transistors 10,12. Thedrain electrodes of the transistors 22,24 are connected to a junction28. A conductive link 30 interconnects the junctions 26 and 28 andthereby the drain and gate electrodes of the respective transistors 22,24.

In FIG. 2 if the input voltage v_(in) is increased from the quiescentvoltage V_(dda)/2 then eventually the current in the PMOS transistor 10reaches zero as the current in the NMOS transistor reaches 4J. In FIG. 3if the input voltage Vin is decreased from the quiescent voltageV_(dda)/2 then eventually the current in the NMOS transistor 12 reacheszero as the current in the PMOS transistor 10 reaches 4J. These twoextreme conditions represent the useful linear range of the class ABtransconductor, that is CMOS transistors 10, 12.

Considering FIGS. 1 to 3, it can be shown that if the quiescent gateoverdrive voltage, V_(gt)=V_(gs)−V_(t), is made equal to V_(t)/2, theanalogue supply voltage is set to V_(dda)=3V_(t) and the quiescent inputvoltage is 3V_(t)/2, then the input voltages v_(in) producing theseextreme conditions are 2V_(t) (FIG. 2) and V_(t), (FIG. 3), and all thetransistors stay saturated between these extremes. The choice representsthe highest V_(gt) and the lowest V_(dda) that can simultaneouslysustain saturated operation over the whole ±4J output signal range. Ifthe V_(dda) rail 14 is generated from a regulator then the externalsupply V_(dd) must be greater than 3V_(t) (=4V_(t)). Use of the systemV_(dd) with this optimum value gives the system with the lowest powerconsumption. A higher V_(dd) increases the power consumption directlywhereas a lower V_(dd) is only possible with a lower V_(gt) which lowersthe signal-to-noise (S/N) ratio and this can only be restored byincreasing the power consumption. Referring to the above table it can beseen that the current technology is naturally near the optimumV_(da)/V_(t) ratio but in the anticipated future technology this ratiois expected to be below the optimum value for this ratio and unless someaction is taken to try and achieve the optimum value a serious increasein power consumption could result if it is desired to maintain orimprove upon the S/N ratio.

Referring to FIGS. 4 to 6, since the basic features of these circuitshave already been described with reference to FIGS. 1 to 3,respectively, then in the interests of brevity FIGS. 4 to 6 will not bedescribed in detail.

Referring to FIG. 4, the gate electrodes of the PMOS transistor 10 andthe NMOS transistor 12 are connected by way of respective conceptual“batteries” 32, 34 to the input junction 18. The batteries 32, 34 have avoltage V_(b). This effectively creates a transconductor with a pair ofcomposite transistors P′ and N′, as shown in broken lines, withthreshold voltages V_(t)′=V_(t)−V_(b). If the circuit is operated from asupply voltage of V′_(dda)=3V′_(t)=3(V_(t)−V_(b)) and setV′_(gt)=V′_(t)/2=(V_(t)−V_(b))/2. In FIG. 4 the quiescent input voltageis 3/2(V_(t)−V_(b)) and the output current is zero.

FIGS. 5 and 6 illustrate the extreme operating conditions for saturatedoperation over the whole ±4J output current range. In the case of thetransconductor consisting of the CMOS transistors 22, 24 conceptualbatteries 36, 38 are coupled respectively between the gate electrodes ofthe transistors 22 and 24 and the junction 26. Thus in FIG. 5, thejunctions 18 and 26 are respectively at voltages 2(V_(t)−V_(b)) and(V_(t)−V_(b)) and the current in the PMOS transistor 10 is zero whereasthe current in the NMOS transistor 12 is 4J. The situation is thereverse in FIG. 6.

The “battery” voltage V_(b) may be designed to give the condition forminimum power consumption despite a non-optimum V_(dd)/V_(t) ratio,namely V_(dd)>3V_(t)(≈4 V_(t)).

FIG. 7 illustrates an implementation of a single-ended class ABtransconductor circuit made in accordance with the present invention.Compared to the conceptual transconductor circuit shown in FIG. 4, the“batteries” are created by voltage drop of equal current I_(p)=I_(n)from respective current sources 40, 42 flowing in resistors 44, 46having a value R_(b). The resistors are decoupled by capacitors 48, 50.The gate electrodes of the transistors 12, 10 are connected to nodes 52,54 located respectively at the junctions of the current sources 40, 42,and the resistors 44, 46. The gate voltages at the nodes 52, 54 arev_(in)+V_(b) and v_(in)−V_(b), as before.

FIG. 8 illustrates an embodiment of a balanced arrangement of the classAB transconductor circuit shown in FIG. 7. Apart from the implementationof a common mode feedback circuit, the balanced arrangement isessentially two parallel single ended arrangements as shown in FIG. 7.Accordingly those parts of the duplicate transconductor (based ontransistors 10′ and 12′) which correspond to the original transconductor(based on CMOS transistors 10, 12) have been referenced with primedcorresponding reference numerals. Also in the interests of brevity onlythose parts of the balanced arrangement not previously described will bedescribed.

The current sources 40, 40′ respectively comprise PMOS transistors 56,56′ whose source-drain paths are connected between the voltage supplyline 14 and the resistor 44, 44′ and whose gate electrodes are biased bya reference voltage V_(ref). The current sources 42, 42′ respectivelycomprise NMOS transistors 58, 58′ whose drain-source paths are connectedbetween the resistor 46, 46′ and the voltage supply line 16. The gateelectrodes are biased by a common-mode feedback circuit comprising equalvalue resistors 60, 62 connected in series between the drain electrodesof the PMOS transistors 56, 56′. A junction 64 of the resistors 60, 62is connected to a node 66 in a conductive link 68 between the gateelectrodes of the transistors 58, 58′. The common feedback path producesthe condition I_(p)=I_(n), sets the input quiescent voltages and createsthe required set of “batteries”.

More particularly the common mode feedback works by the PMOS transistors10, 10′ creating bias currents Ip which flow into the nodes 52, 52′. Thetransistors 12, 12′ create bias currents I_(n) which flow into nodes 52,52′ by way of the nodes 54, 54′. If I_(n)>I_(p) then the nodes 52, 52′and 66 fall until I_(n)=I_(p). Conversely, if I_(n)<I_(p) then the nodes52, 52′ and 66 rise until I_(n)=I_(p), Consequently the common-modefeedback circuit is stable with I_(n)=I_(p). This is not disturbed bydifference mode input voltages as these do not disturb the voltage atthe node 66. Under quiescent conditions, and with all the transistorsdesigned with equal gate overdrive voltages V_(gt)=(V_(t)−V_(b))/2, thenthe voltages at the nodes 52, 52′ areV_(gs 12,12′)=V_(t)+V_(gt)=(3V_(t)−V_(b))/2, and the voltages at theinputs are V_(Q)=V_(gs 12,12′)−V_(b)=(3V_(t)−V_(b))/2=V_(dda)/2. So thecommon-mode feedback circuit creates a mid-rail quiescent input voltage.Under signal conditions with a differential input voltage v_(in), theinput nodes are at ν_(in) ⁺=V_(Q)+ν_(in)/2 and ν_(in) ⁻=V_(Q)−ν_(in)/2,and the gate voltages at the nodes 52, 54 and the nodes 54′ and 52′ areν_(in) ⁺−V_(b),ν_(in) ⁺+V_(b) and ν_(in) ⁻V_(b),ν_(in) ⁻+V_(b),respectively.

It is desirable that the resistors 60, 62 should have a value R_(cm)such that R_(cm)>>1/G_(m) to avoid significant loading of the inputnodes.

FIG. 9 illustrates another embodiment of a class AB transconductorcircuit made in accordance with the present invention. The maindifference between the embodiments shown in FIGS. 8 and 9 is in theimplementation of the common mode feedback circuit. Accordingly in theinterests of brevity a detailed circuit description will not beprovided.

Instead of the common mode feedback arrangement shown in FIG. 8 in whichthe resistors 60, 62 are connected in series between the drainelectrodes of the PMOS transistors 56, 56′ and a connection from ajunction of these resistors is connected to the gate electrodes of theNMOS transistors constituting the current sources 42,42′, there are nosimilar connections to the drain electrodes of the PMOS transistors 56,56′ but instead the current sources 42, 42′ comprise respectively a NMOStransistor 70, 70′ having its source electrode connected to the drainelectrode of a NMOS transistor 72, 72′ and its drain electrode coupledto the resistor 46, 46′. The source electrodes of the NMOS transistors72, 72′ are connected to the power supply rail 16. Gate electrodes ofthe NMOS transistors 72, 72′ are connected respectively to the drainelectrodes of the NMOS transistors 70, 70′. Junctions of the sourceelectrodes of the NMOS transistors 70, 70′ and the drain electrodes ofthe NMOS transistors 72, 72′ are interconnected by a conductive link 74.The gate electrodes of the PMOS transistors 56, 56′ are biased by afirst reference voltage source V_(ref1) and the gate electrodes of theNMOS transistors 70, 70′ are biased by a second reference voltage sourceV_(ref2).

In operation the NMOS transistors 72, 72′ are triode operatedtransistors which means that their resistances can be altered by varyingthe bias voltages on their gate electrodes. If, for example, the voltageat the junction 18′ is much higher than the voltage at the junction 18,the gate voltage on the NMOS transistor 72′ increases causing theresistance to decrease and the drain-source current to increase untilI_(p)=I_(n).

In the differential drive mode, the resistances of the transistors 72,72′ are short circuited by the conductive link 74 causing the sum of thedifferential currents to be zero. The common mode operation is obliviousto the input signals.

The balanced class AB transconductor circuits are frequently used ingyrator filters, which generally exclude op-amps, employed as IF filtersand channel filters in low voltage transceivers. FIG. 10 illustrates anembodiment of a transceiver in which a polyphase channel filter CF inthe receiver section Rx comprises two fifth order bandpass filters, onefor each of the quadrature related phases.

An antenna 76 is coupled to a low noise amplifier (LNA) 78 in thereceiver section Rx. An output of the LNA 78 is coupled by way of asignal divider 80 to first inputs of quadrature related mixers 82, 84. Alocal oscillator signal generated by a signal generator 86 is applied toa second input of the mixer 82 and, by way of a ninety degree phaseshifter 88, to a second input of the mixer 84. Quadrature relatedoutputs 1, Q, respectively, from the mixers 82, 84 are applied to thepolyphase channel filter CF which passes the wanted quadrature relatedsignals to respective analogue-to-digital converters 90, 92. The digitaloutputs from the A-to-D converters 90, 92 are applied to a digitaldemodulator 94 which provides an output signal on a terminal 96.

The transmitter Tx comprises a digital modulator 98 which includes adigital-to-analogue converter (not shown) providing an analogue signalto a mixer 100 for frequency up-conversion to the required transmissionfrequency. A power amplifier 102 amplifies the frequency up-convertedsignal and supplies it to the antenna 76.

The transceiver including the channel filter CF may be fabricated as anintegrated circuit using known low voltage CMOS processes.

In the present specification and claims the word “a” or “an” precedingan element does not exclude the presence of a plurality of suchelements. Further, the word “comprising” does not exclude the presenceof other elements or steps than those listed.

From reading the present disclosure, other modifications will beapparent to persons skilled in the art. Such modifications may involveother features which are already known in the design, manufacture anduse of class AB transconductor circuits and component parts therefor andwhich may be used instead of or in addition to features alreadydescribed herein. Although claims have been formulated in thisapplication to particular combinations of features, it should beunderstood that the scope of the disclosure of the present applicationalso includes any novel feature or any novel combination of featuresdisclosed herein either explicitly or implicitly or any generalisationthereof, whether or not it relates to the same invention as presentlyclaimed in any claim and whether or not it mitigates any or all of thesame technical problems as does the present invention. The applicantshereby give notice that new claims may be formulated to such featuresand/or combinations of such features during the prosecution of thepresent application or of any further application derived therefrom.

1. A class AB transconductor circuit comprising complementary PMOS andNMOS transistors having their source-drain paths connected in seriesbetween first and second voltage supply rails, an output terminalcoupled to a junction of said series connected source-drain paths, andtheir gate electrodes coupled to an input terminal by way of respectivefirst and second paths, wherein first and second bias voltage supplymeans are respectively provided in the first and second paths.
 2. Atransconductor circuit as claimed in claim 1, characterised in that thefirst and second bias voltage supply means comprise first and secondseries connected resistors coupled between a first current sourceconnected to the first voltage supply rail and a second current sourceconnected to the second voltage supply rail, and in that the inputterminal is connected to a common junction (18) of the first and secondseries connected resistors.
 3. A transconductor circuit as claimed inclaim 2, characterised in that the first and second resistors aredecoupled by respective capacitances.
 4. A transconductor circuit asclaimed in claim 2, characterised in that the gate electrode of the PMOStransistor is coupled to a junction of the second resistor and thesecond current source and in that the gate electrode of the NMOStransistor is coupled to a junction of the first resistor and the firstcurrent source.
 5. A balanced class AB transconductor circuit comprisingfirst and second transconductor circuits as claimed claim 1, balancedinputs being applied to the respective input terminals and balancedoutputs being derived from the respective output terminals.
 6. Abalanced class AB transconductor circuit comprising first and secondtransconductor circuits as claimed in claim 4, characterised in thatbalanced inputs are applied to the respective input terminals, in thatbalanced outputs are derived from the respective output terminals, inthat the first current sources of each of the first and secondtransconductor circuits comprise externally biased PMOS transistors, inthat the second current sources of each of the first and secondtransconductor circuits comprise NMOS transistors, and in that a commonmode feedback circuit is provided, the common mode feedback circuitcomprising first and second substantially equal value resistors coupledin series between drain electrodes of the externally biased PMOStransistors and a connection from a common junction of the first andsecond substantially equal valued resistors to the gate electrodes ofthe NMOS transistors.
 7. A balanced class AB transconductor circuitcomprising first and second transconductor circuits as claimed in claim4, characterised in that balanced inputs are applied to the respectiveinput terminals, in that balanced outputs are derived from therespective output terminals, in that the first current sources of eachof the first and second transconductor circuits comprise externallybiased PMOS transistors, in that the second current sources of each ofthe first and second transconductor circuits comprise externally biasedNMOS transistors, and in that common mode feedback circuit means areprovided, the common mode feedback circuit means comprising for each ofthe first and second transconductor circuits a triode operated NMOStransistor having its drain-source path coupled between the sourceelectrode of the externally biased NMOS transistor and the secondvoltage supply rail and its gate electrode connected to the drainelectrode of the externally biased NMOS transistor; the sourceelectrodes of the externally biased NMOS transistors beinginterconnected.
 8. An integrated circuit comprising a balanced class ABtransconductor circuit as claimed in claim
 5. 9. An integratedtransceiver comprising a class AB transconductor circuit as claimed inclaim 1.